1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices and a method of testing the same, and more specifically relates to a semiconductor integrated circuit device and a method of testing the same, wherein a test flow effecting decision as to whether a semiconductor integrated circuit device, such as an LSI chip conforms or is defective in a wafer test, and a defective article recognition circuit for realizing the test, flow are provided.
2. Description of the Prior Art
In recent years, in the field of multimedia equipments, for data processing of high degree attendant on processing of digital signals, devices of high performance have been required. On the other hand, in order to meet request of portability, specification which can not be easily attained by conventional semiconductor products is required in that semiconductor devices must be of small size and low consumption power. For such request, in order to intend low consumption power of a system and to reduce a board area, a hybrid IC such as a DRAM containing logic IC (hereinafter referred to as "eRAM (embedded RAM) logic IC") in which DRAM and logic are formed in the form of one chip has been developed. The logic generally means a logic circuit where inputted data are subjected to logic operation and outputted, and in the logic of eRAM type, the operation result at the midway of the logic operation is once stored in the DRAM and the stored operation result is drawn afterward and subjected to the operation processing.
When such a hybrid IC is manufactured, a wafer test must be performed so as to effect decision that IC is conformed or defective before the shipment.
In general, a chip judged defective in the wafer test is marked with ink and then advanced to assembly in next process, and in the case of the hybrid IC, the DRAM unit and the logic unit must be tested in wafer test respectively. This is because a tester used in testing a general-purpose DRAM is different from that used in testing a logic IC, and in similar manner to this, in order to test the DRAM unit or the logic unit individually in the above-mentioned eRAM, the DRAM unit and the logic unit must be tested using individual testers.
When the DRAM unit and the logic unit are tested, if the ink marking to the defective chip is executed at finishing of test of either unit, a problem is produced that a wafer jig (probe card) may be flawed at testing of another unit. For example, consider that the test is performed in the order of the test of the DRAM unit and the test of the logic unit. Here the probe card is allowed to contact a needle being a part thereof with a pad within a chip and thereby performs test in giving an electric signal.